|The principle of operation of a single-conversion superhet receiver is shown in Figure 1. The desired input signal f1 is mixed with a local oscillator signal f0. This results in a signal containing the sum and difference of the two input frequencies. The intermediate frequency (IF) signal is obtained by applying the mixer output to a filter tuned to the frequency of the difference signal. This signal is then amplified and applied to a detector.|
There are two possible values for f1 which satisfy
the relationship |f0 - f1| = fIF
; these are:
f1 = f0 - fIF
f1 = f0 + fIF
The receiver therefore has an input filter to select whichever of these is required. Tuning of the receiver is accomplished by tuning the input filter and the local oscillator simultaneously, in such a way that f0 - f1 is a constant. A receiver in which f0 = f1 + fIF is said to operate with 'oscillator high'. A receiver in which f0 = f1 - fIF is said to operate with 'oscillator low'. The oscillator low system has the disadvantage that when the input frequency is twice the IF, the local oscillator is tuned to the IF channel and the IF amplifier is blocked. Consequently, the vast majority of general-coverage radio receivers operate with oscillator high. To obtain a digital presentation of the frequency to which such a receiver is tuned, it is necessary to measure the frequency of the local oscillator and subtract the IF from it before displaying the result.
The digital readout described in this article was built for an RCA AR88 receiver, which was used as the interpolation receiver for a Microwave Spectrometer at Bristol University some years ago. The requirements for microwave spectroscopy are somewhat different from those for short-wave listening, but adapting the circuitry for the latter purpose is trivial. The AR88 is an oscillator high receiver having an IF of 455 kHz.
Figure 2 above shows circuitry which was built into the receiver
in order to provide an oscillator output. This circuit is a non-linear
buffer amplifier, with a high input impedance, which takes a
signal directly from the anode (plate) of the oscillator valve.
The 2-10 pF trimmer capacitor provides some measure of control
over the amplifier frequency response, and is best adjusted by
experimenting with the receiver in conjunction with the digital
counter and ensuring that satisfactory triggering occurs at all
frequencies. It should be noted however, that inclusion of the
buffer circuit necessitates complete re-tracking and alignment
of the oscillator. The compensation trimmer should therefore
only be adjusted prior to final receiver alignment. The rectifier
and 2200 μF smoothing capacitor can be mounted in the power
supply section of the receiver chassis. The remainder of the
components should be mounted on a small board inside the under-chassis
oscillator compartment, and as close as is practicable to to
the oscillator valve anode connection. Care should be taken to
minimise the added stray capacitance at the oscillator anode;
this affects tuning of the oscillator and too much may make the
receiver impossible to realign. The oscillator output is brought
to a BNC socket on the back of the chassis. The signal is rich
in harmonics, and although none of these fall on frequencies
which the AR88 can hear, a good quality shielded cable is recommended
for the sake of any nearby VHF equipment.
Re-tracking of the oscillator is usually a straightforward matter once the frequency counter has been built; for the simple reason that the counter will always display the frequency to which the receiver is tuned, and re-tracking becomes a matter of making the digital readout agree with the tuning dial. The AR88 is an example of a receiver which uses two-point tracking, ie., each oscillator range has two adjustable parameters, namely the inductance of the tuning coil (dust iron slug) and the fixed capacitance in parallel with the tuning capacitor (trimmer). In this case, perform the following procedure (for each range of the band-switch): swing the tuning capacitor to a point close to the low frequency end of the band and adjust the coil to make the dial reading agree with the counter. Then swing to a point close to the high frequency end of the band and adjust the trimmer capacitor to make the dial agree with the counter (choose an HF setting point about 10% of the dial rotation in from the band edge, and a LF setting point at or close to the band edge). Repeat this procedure over and over again (Keep repeating the mantra "LF-L, HF-C"). After a few rounds of iteration the required adjustments will become so small that they are no longer worthwhile. While you are at it, you might as well also peak the RF and Mixer stages for maximum signal strength (same procedure: LF - tweak the coil, HF - tweak the trimmer), and thereby achieve a complete front-end realignment. Note however, that not all receivers use the simple 2-point tracking scheme outlined above. In particular, you may encounter circuits which have an adjustable capacitance (called padding) in series with the tuning capacitor. If the coil has no adjustable slug, 2-point tracking is achieved by adjusting the trimmer at the high end (as before) and the padder at the low end. If the circuit has a slug, a trimmer, and a padder, 3-point tracking is possible, and for proper realignment it is advisable to follow the procedure laid out in the receiver manual. If no manual is available, observe that the capacitance added by the oscillator take-off circuit can generally be subtracted from the trimmer. You might also consider choosing a take-off point in such a way that the added capacitance is definitely in parallel with the trimmer (eg, if the trimmer is connected across the grid circuit, try taking the signal from the grid). You may then achieve a realignment at least as good as before you started by confining your adjustments to the trimmer only. A detailed discussion of superhet tracking is given in the 'Radio Designer's Handbook' (aka 'Radiotron Designers Handbook', ed. F Langford-Smith) 4th edition or higher (1954-1957).
Refer to the circuit diagram, Figure 3 (164K GIF) before reading this section.
The counter shown in Fig. 3 is designed for use with the modified AR88 receiver, or any similar receiver having an IF of less than 99.999 MHz. An obvious additional limitation is that the maximum local oscillator frequency must not exceed the maximum clocking speed of the counter; a requirement which depends on the speed of the device used for the sampling gate, and on the speed of the first chip in the counting chain. In the existing design, the least significant digit of the display is in ones of kHz; but this can easily be extended to 100 Hz, or even 10 Hz if the sampling rate is reduced. The counter does not explicitly perform a subtraction to obtain the listening frequency from the oscillator frequency: Instead, the count register (5 x 74LS196) can be programmed by means of thumbwheel switches, so that it resets to a non-zero number before the start of each count. If, as in the case when used with the AR88, the count register is set to 99545, the first 455 pulses cause the register to contain 00000, since the 1 of 100000s is lost in the overflow. Subsequent pulses increment the counter, so that the result displayed at the end of the counting period is the oscillator frequency minus 455 kHz, i.e. the true receiver frequency. In general, to program the register correctly, for an oscillator high receiver:
Thumbwheel setting = 100000 - IF in kHz.
If the counter is extended to read out to 100 Hz, an extra thumbwheel switch can be added, and the thumbwheel setting becomes; 1000000 - IF in 100s of Hz (e.g., 4550).
For an oscillator high receiver, the thumbwheels are merely set to the IF in multiples of the least significant decimal place.
Note that you can dispense with the thumbwheel switches if you hard wire the binary-coded decimal (BCD) for the receiver IF into the counter preset inputs. The thumbwheel switches were provided in the original so that the counter could easily be adapted to work with a different HF receiver (with a different IF) if the AR88 should fail; but for most purposes, a set of DIP switches on the circuit board should be adequate for this purpose. The ability to turn off the IF offset is useful however, because the counter then becomes an ordinary DFM; and it is a relatively straightforward matter to provide a single switch to disable the offset and divert the counter input to a socket on the front panel. One way to disable the offset is to connect the anode of a diode to each of the preset inputs, and join all of the cathodes together. Connect the cathodes to +5V when the offset is required, and to ground when the offset is not required. Ordinary 1N4148 diodes should be adequate, although it may be necessary to increase the pull-up resistors to 10 kΩ, to ensure that the preset inputs can fall reliably below 0.8 V.
The frequency counter derives its timing waveforms from an internal 500 kHz crystal oscillator. The output of this oscillator is divided by 250, in three 7490 integrated circuits, to provide a 2 kHz signal which is applied to the timing waveform generator. Any other method for generating an accurate 2 kHz square wave is of course acceptable. The operation of the timing waveform generator is described in Figure 4 (below).
The Q outputs of the two quinary counters shown above are gated
together to produce the three housekeeping signals; 'Gate', 'Strobe',
and 'Reset'. The gate signal causes the amplified input signal
to be applied, via the signal gate (¼ 74S00), to a 74S196
divide-by-ten counter. The signal gate opens for 10ms, during
which time counting occurs, then closes for 2.5ms, during which
time the strobe signal loads the display register (2 ×
74LS377, 1 × 7475)), and then the reset signal loads the
count register according to the thumbwheel settings. The display
is therefore updated every 12.5 ms (80 Hz refresh rate).
The counter at the fast end of the count register is a 74S196 part, capable of clocking at 100 MHz, and the signal gate correspondingly is a 74S00. These parts are now obsolete, and although the 74S00 can be replaced by a 74F00, the 74_196 is unfortunately unavailable in high-speed versions. This should not be a problem with general coverage HF receivers with a low IF because 74LS series parts are officially capable of clocking up to at least 30 MHz and can therefore be used as substitutes. With device selection, 74LS series parts manufactured from the mid 1970s onwards can be found that will clock at speeds in excess of 70 MHz, and the 1977 spec. Motorola 74LS196 is guaranteed to clock at 45 MHz min., with 60 MHz being typical. If higher speeds than that are required, note that the 74_196 parts were selected for their asynchronous preset facility, and can therefore (with appropriate changes to the circuit) be replaced by a variety of counters depending on whether or not an offset is required at the digit in question. In particular, the '90, '390, and '160A can be used in situations where no offset is needed, and the '190 or '192 can be used when an offset is required. The '160A , '190 and '192 are available in 74F series (100 MHz) TTL versions.
Note that in the original circuit, the status of the 74S196 is never displayed, and it acts as a pre-scaler. It does receive a reset signal however, because that resolves the ambiguity of ±1 in the least significant digit, due to lack of phase coherence between the gate signal and the input signal. Effectively, the ambiguity is moved to an undisplayed digit in this application (display to nearest 1 kHz), but for short wave listening, a display to 100 Hz will be required and the ambiguity will be present. To modify this circuit for readout to 100 Hz; simply extend the display register by 4 bits (ie., change it to 3 x 74LS377), and add an extra display decoder and display device for the first (right-most) chip in the count register. If a 74LS196 is used in this position; connect the preset (load) and reset (clear) inputs as for the chips to the left, and provide it with a thumbwheel or DIP switch, or hard-wire the offset, as necessary.
If 100 MHz (typ.) input clocking is required with an offset at the fast end of the count register, a suitable approach would be to modify the circuit to use a 74F192 counter in first position. The '192 is a synchronous up/down counter, which can be set to count upwards by connecting the 'down-clock' input to +5 V and applying the output of the sample gate to the 'up-clock' input. When using this chip, connect the reset (clear) input to ground, and the preset (load) input to the 'NOT-reset' line. The clock input of the next chip in the count register chain should be connected to the QD output (the ripple carry output being of the wrong polarity to trigger the '196). Note that pre-loading 0000 has the same effect as a reset, so simply ground all of the data inputs if no offset is required.
If you want to read out to 10 Hz (completely pointless with equipment like the AR88) change the reference frequency from 2 kHz to 200 Hz and extend the display to another digit (moving the decimal point appropriately). The refresh rate will then be 8 Hz, which is considerably less ergonomic than 80 Hz, but more suitable if you are forced to use 7-segment displays instead of the original Nixies. The problem with 7-segment LEDs is that they read nonsense when flashing rapidly between two numbers, unlike Nixies, which just give the two numbers superimposed. The best option with 7-segments therefore is to opt for 8 Hz sampling, but with synchronous prescaling as in the original design, and a readout to 100 Hz.
The input amplifier is a wide-band non-linear circuit. The input signal is limited, before amplification, by means of two 1N6263 Schottky (semiconductor-metal junction) diodes connected back to back. The final transistor in the amplifier chain is operated as a non-saturating switch, the Schottky diode between base and collector being present to prevent saturation (which entails a speed penalty in the recovery). The choice of Schottky diode is not critical, and the current more readily available 1N5712 should also be suitable. The input to the amplifier is provided with two adjustments; input level and HF compensation. These are used to obtain satisfactory triggering of the counter on all frequencies covered, although below 50 MHz, HF compensation is unnecessary and the trimmer capacitor may be omitted or set to minimum. The counter input impedance is nominally 50 Ω, and the 56 Ω terminating resistor must be a non-inductive type.
Information on using Nixie tubes is given in a separate article. The small inverter modules (5 V in, 180 V out) are now difficult to obtain, and it may be necessary to use a conventional HT supply. When designing an HT supply, make sure that the voltage cannot float above about 200V off load, since the 74141 output transistors may be damaged if this voltage is significantly exceeded. Alternatively, you may replace the display with 7447s and 7-segment LEDs, and reduce the design refresh rate to 8 Hz, as mentioned above. Needless to say, the counter can radiate spurious signals in the receiver passband, and so a metal box acting as a Faraday cage is mandatory. The original design had no RF filter in the mains socket, which was fine for its intended purpose, but a filter must be added if the counter is to be part of a radio installation.
The original divider chain used 5 × 7490 ICs. The chip count can be reduced by replacing pairs of 7490s with 74LS390s. All of the ICs except the 74141 and the 74S series parts can be replaced with 74LS series ICs. The 74S00 should be replaced with a 74F00. The 74S196 can be replaced with a 74LS196 if a reduction in clocking speed is acceptable, or the circuit can be modified to use a 74F192 in its place (as described above).
Accuracy of Readout:
Error in the displayed frequency is primarily due to any discrepancy between the desired and the actual frequency of the reference oscillator. This error is given by;
Display error = Input freq × fractional error in reference freq.
I.e. for oscillator high;
Display error = (Display freq + IF) × Fractional error in reference freq.
The crystal oscillator can be expected to have a short and long term stability of better than ±20 ppm, which gives a worst case accuracy of ±600 Hz at an input frequency of 30 MHz. In practice, the reference frequency can be adjusted to make the readout agree with one of the many frequency standards broadcasts, in which case a short term improvement of at least an order of magnitude is easily obtainable. The stability of the oscillator can, of course, be improved by operating it inside a constant-temperature oven.
Further design issues:
The synchronous prescaler design of the original suffers from rounding error in the last digit, since rounding up is not attempted in the event that the non-displayed digit (10ths of kHz) is greater than 4. The problem can be overcome by pre-setting the prescaler to BCD 5 (0101), rather than re-setting it to zero as was originally done. This modification only applies to the synchronous prescaler (if used). It is not required if the counter chip is to be connected to a display.
When simple counters of this type are used without synchronous prescaling, the display has an ambiguity of ±1 in the last digit, and will generally flicker between the two possibilities. This ambiguity can be removed by synchronising the reference oscillator to the incoming pulses: ie., the counter is made to complete all operations up until the point where it will take one more pulse from the oscillator to cause the gate to open. The oscillator is then stopped and allowed to settle, and then restarted upon detection of an input event. In this way the display will always show the lower of the two possibilities; thus eliminating a slightly irritating effect at the cost of introducing a small bias into the sampling method (and much additional complexity). Some readers may have come across a much simpler synchronisation method, as described in the 'TTL Cookbook', by Don Lancaster (1st edition); but the circuit has obviously never been tried, the argument behind it is fallacious, and it will not work.
Note that this counter design displays a frequency referenced to the middle of the IF passband. If a BFO or CIO is used, the displayed frequency will only correspond to the zero-beat frequency when the CIO is also tuned to the middle of the IF passband. Accounting automatically for the CIO tuning can accomplished by using up/down counters in the count register; obtaining the receiver frequency corresponding to zero beat by first counting down from a CIO input, and then counting up from a local oscillator input (or vice versa in the case of a band-inverting multiple conversion receiver). This technique is used in the author's 'Digital Readout and All-Mode Adapter for the Racal RA17'.
References and Further Reading:
'Radio Designer's Handbook' ('Radiotron Designer's Handbook' in Australian editions), ed. F Langford-Smith. 4th edition, revised 4th impression with addenda, Iliffe, London,1957.
D.W. Knight, 1984, 2000, 2008, 2014.
Updated: 29th Oct. 2000. + 24th Jan. 2008. 4th Sept. 2014. Version 1.01.